3D Stacking - Wafer to Wafer

The current and future demands of cell phones, pocket PC's and other consumer devices are pushing industry technologies into maximum functional integrations in the smallest possible footprint, lowest profile and lowest cost packages available. This economy can only be achieved by 3D stacking die or stacking packages or a mix of both.

The benefits of 3D integration are numerous but they have been plagued by problems associated with the integration of off-the shelf chips from multiple suppliers. MCSP's glass sheet redistribution layer solves the mixed integration dilemma without the need for wire-bonding or expensive packaging solutions. Designers have higher design flexibility, lower costs (including lower NRE) and a shorter time to market with lower risk. Now the integration of different silicon process technologies can be fully integrated into one stacked functional technology - CMOS, memory SiGe and MEMs, SDRAM, ASIC, GPU, Flash, digital and RF/analog chips that were previously impossible can be smoothly integrated into achievable highly value-added devices.