The primary technology of the company is a WLCSP process called Metallized Conductor Chip Scale Package (MCSP), which performs all IC packaging steps at the wafer level. The MCSP technology employs a glass sheet as substrate that is attached to a semiconductor wafer to form a redistribution layer directly on the wafer surface. The redistribution layer connects the fine-pitch bond pads on the semiconductor wafer to large-pitch interconnect pads on the glass sheet. The reduction of IC packaging steps from the traditional front and back- end processes to the wafer level significantly reduces production costs and improves yield.

Vias, drilled through the glass sheet to corresponding locations on the IC bond pads, create this second level redistribution layer. Thin film patterning on the glass prior to wafer attachment creates an array of traces, passive component level incorporation and 3D stacking capabilities. Independent of the semiconductor wafer this glass layer can be tested and component values trimmed according to specific requirements prior to attachment directly to the semiconductor wafer surface.

The patterned glass sheet is attached to a wafer with an optical adhesive, which can be selectively applied. These void areas can be used as optical windows or protective coverings in CMOS, MEMS and VCSEL device applications. Also the voids can be back filled with inert gases for specific applications. Once the glass and wafer are attached using very low temperature curing optical adhesives metal is deposited, which interconnects the IC bond pads and the metallized traces on the pre-tested glass sheet. The next level interconnect can be applied; either solder balls are attached or pads are created for further interconnect technologies. The completed wafer-glass structure is sawn and diced into individual packages. The resulting IC package using the MCSP process is equivalent to the original die size and is smaller and thinner than most conventional packages. The MCSP process is superior to other competing WLCSP processes because it uses industry-standard fabrication techniques, has lower manufacturing costs, an efficient development flow and short assembly cycle time. The company is in the process of expanding filings on several current MCSP patents.

Several troublesome industry applications are ideal for the MCSP technology. They are hermetically sealed chip-scale packages, filter networks in close proximity to IC processors, 3D stacking, Silicon-On-Insulator (SOI), and OptoElectronic IC (OEIC) data transmission. Along with standard integrated circuit packaging using WLCSP, the company has focused development activities on hermetic sealing at the wafer level, thin-film and thick-film passive component deposition, 3D stacking, SOI, and Optoelectronic WLCSP technologies